1. Field of Invention
The present invention relates to the field of computer systems. More particularly, this invention relates to a system and method for enhancing memory to memory copies in computer systems.
2. Description of Related Art
A computer system typically includes a processor and a memory having a main memory and a cache memory for storing data and instructions for the processor. The cache memories store blocks of data and/or instructions that are received from the main memory. Typically, instructions from the main memory that are used by the processor are stored in the instruction cache and the data for that particular instruction is stored in the data cache. The computer system utilizes the processor to complete these instructions by executing commands that are part of these instructions.
One instruction that is frequently executed by the processor is a memory-to-memory copy. The memory-to-memory copy involves copying a data block from a first location in memory to a second location in memory. When a block copy is requested, the processor allocates address space in the second location for the data block, reads the data from the first location, and writes the data to the second location.
The copying of memory through the execution of instructions in the processor consumes processor time that could otherwise be used to execute other instructions. For example, when a number of memory requests are made, the processor is busy executing these requests for a significant amount of time. This reduces the amount of instructions that a particular processor can execute in a given time period.
It should therefore be appreciated that there remains a need for a computer system that can perform memory-to-memory copies without using a significant amount of the processor""s resources. The present invention fulfills this need.
The present invention is embodied in a computer system, and related method, that includes system control units that enhance memory to memory copy transactions. The computer system includes a processor, a source system control unit coupled to the processor, a destination system control unit coupled to the source system control unit, a source memory coupled to the source system control unit, and a destination memory coupled to the destination system control unit.
The related method includes transmitting from the processor to the source system control unit a plurality of memory-to-memory copy transactions where each transaction includes a source address and a destination address. A lookup operation is performed on the destination address to determine the destination system control unit that controls access to the destination memory which contains the destination address. A number of data blocks located at the source address in the source memory are retrieved and transmitted to the destination address. The number of data blocks are stored at the destination address in the destination memory.
Other features and advantages of the present invention will be apparent from the detailed description that follows.